In these days, a very high data transfer rate is required of data transfer between different semiconductor devices, for example, between a CPU and a memory. To implement this, the amplitude of an input/output signal is becoming ever smaller. If the amplitude of the input/output signal becomes smaller, the requirement for precision in the impedance of the output buffer becomes extremely strict.
The output buffer impedance not only is fluctuated with variable process conditions at the time of manufacture but also is changed during the time of field use under the influences of changes in the ambient temperature or in the power supply voltage. For this reason, should high precision be required of the output buffer impedance, an output buffer having a function of impedance adjustment is used. Such impedance adjustment for the output buffer is performed using a circuit called a ‘calibration circuit’ in general.
A replica buffer having the same configuration as that of the output buffer is contained in the calibration circuit. In performing a calibration operation, a voltage appearing at a calibration terminal is compared to a reference voltage, in a state where an external resistor is connected to the calibration terminal, thereby adjusting the impedance of the replica buffer. The impedance of the output buffer is set at a desired value by having the adjustment contents of the replica buffer reflected in the output buffer.
In the sequence of the calibration operations, a plurality of adjustment operations, each including the steps of voltage comparison and update of the impedance of the replica buffer, are carried out, thereby causing the impedance of the output buffer to approach towards a desired value.
However, the voltage comparison or the change in the impedance of the replica buffer in the calibration operation takes some time. Thus, if the external clock frequency is high, it is not possible to execute an adjustment operation each time an external clock is activated. In such case, it may be feasible divide the frequency of the external clock to generate an internal clock of a lower frequency and to execute the adjustment operation in synchronization with the lower frequency achieved. For such a case that, in connection with such calibration circuit, the number of the adjustment operations that may be carried out in one calibration time interval is small, there is disclosed in Patent Literatures 1 and 2 a technique that allows impedance adjustment to be performed more reliably.